Phase-change memory via a phase-changeable self-confined nano-filament.

Phase-change memory (PCM) has been considered a promising candidate for solving von Neumann bottlenecks owing to its low latency, non-volatile memory property and high integration density1,2. However, PCMs usually require a large current for the reset process by melting the phase-change material into an amorphous phase, which deteriorates the energy efficiency2-5. Various studies have been conducted to reduce the operation current by minimizing the device dimensions, but this increases the fabrication cost while the reduction of the reset current is limited6,7. Here we show a device for reducing the reset current of a PCM by forming a phase-changeable SiTex nano-filament. Without sacrificing the fabrication cost, the developed nano-filament PCM achieves an ultra-low reset current (approximately 10 µA), which is about one to two orders of magnitude smaller than that of highly scaled conventional PCMs. The device maintains favourable memory characteristics such as a large on/off ratio, fast speed, small variations and multilevel memory properties. Our finding is an important step towards developing novel computing paradigms for neuromorphic computing systems, edge processors, in-memory computing systems and even for conventional memory applications.

Linear conductance update improvement of CMOS-compatible second-order memristors for fast and energy-efficient training of a neural network using a memristor crossbar array.

Memristors are two-terminal memory devices that can change the conductance state and store analog values. Thanks to their simple structure, suitability for high-density integration, and non-volatile characteristics, memristors have been intensively studied as synapses in artificial neural network systems. Memristive synapses in neural networks have theoretically better energy efficiency compared with conventional von Neumann computing processors. However, memristor crossbar array-based neural networks usually suffer from low accuracy because of the non-ideal factors of memristors such as non-linearity and asymmetry, which prevent weights from being programmed to their targeted values. In this article, the improvement in linearity and symmetry of pulse update of a fully CMOS-compatible HfO2-based memristor is discussed, by using a second-order memristor effect with a heating pulse and a voltage divider composed of a series resistor and two diodes. We also demonstrate that the improved device characteristics enable energy-efficient and fast training of a memristor crossbar array-based neural network with high accuracy through a realistic model-based simulation. By improving the memristor device's linearity and symmetry, our results open up the possibility of a trainable memristor crossbar array-based neural network system that possesses great energy efficiency, high area efficiency, and high accuracy at the same time.

The gate injection-based field-effect synapse transistor with linear conductance update for online training.

Neuromorphic computing, an alternative for von Neumann architecture, requires synapse devices where the data can be stored and computed in the same place. The three-terminal synapse device is attractive for neuromorphic computing due to its high stability and controllability. However, high nonlinearity on weight update, low dynamic range, and incompatibility with conventional CMOS systems have been reported as obstacles for large-scale crossbar arrays. Here, we propose the CMOS compatible gate injection-based field-effect transistor employing thermionic emission to enhance the linear conductance update. The dependence of the linearity on the conduction mechanism is examined by inserting an interfacial layer in the gate stack. To demonstrate the conduction mechanism, the gate current measurement is conducted under varying temperatures. The device based on thermionic emission achieves superior synaptic characteristics, leading to high performance on the artificial neural network simulation as 93.17% on the MNIST dataset.

Reliable multilevel memristive neuromorphic devices based on amorphous matrix via quasi-1D filament confinement and buffer layer.

Conductive-bridging random access memory (CBRAM) has garnered attention as a building block of non-von Neumann architectures because of scalability and parallel processing on the crossbar array. To integrate CBRAM into the back-end-of-line (BEOL) process, amorphous switching materials have been investigated for practical usage. However, both the inherent randomness of filaments and disorders of amorphous material lead to poor reliability. In this study, a highly reliable nanoporous-defective bottom layer (NP-DBL) structure based on amorphous TiO2 is demonstrated (Ag/a-TiO2/a-TiOx/p-Si). The stoichiometries of DBL and the pore size can be manipulated to achieve the analog conductance updates and multilevel conductance by 300 states with 1.3% variation, and 10 levels, respectively. Compared with nonporous TiO2 CBRAM, endurance, retention, and uniformity can be improved by 106 pulses, 28 days at 85°C, and 6.7 times, respectively. These results suggest even amorphous-based systems, elaborately tuned structural variables, can help design more reliable CBRAMs.